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From: mgregory@flash.pax.tpa.com.au (Martin John Gregory)
Newsgroups: sci.electronics
Subject: HELP: MC146818A Real Time Clock Standby Mode
Date: 20 Apr 1993 17:40:49 +0930
Organization: PAX - Public Access Unix (Adelaide)
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Message-ID: <1r0b69INN5ct@flash.pax.tpa.com.au>
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I am having trouble obtaining the specified standby current drain from
a MC146818A Real Time Clock.  Has anyone out there had some experience
in doing this?  The specs call for a few sequences to be met before
standby mode is activated, and are a bit hard to decipher on that, but
I thought that I had it worked out.  However, with a 32kHz crystal the
lowest current drain I can acheive at 3.7V Vcc is 150uA.  This is
three times the specified MAXIMUM under the conditions I am attempting
to create.

I have done the following things:

1) Made sure that RESET/ is asserted for Trlh after powerup, and AS is
   low during this time.


2) Made sure that there is a cycle on AS after the negation of RD/ or
   WR/ during which STBY/ was asserted.

What am I doing wrong?

Thanks very much,

Martin.
