Xref: cantaloupe.srv.cs.cmu.edu sci.electronics:53844 comp.lsi:2775
Path: cantaloupe.srv.cs.cmu.edu!crabapple.srv.cs.cmu.edu!fs7.ece.cmu.edu!europa.eng.gtefsd.com!howland.reston.ans.net!zaphod.mps.ohio-state.edu!uwm.edu!caen!uunet!utcsri!eecg.toronto.edu!ravin
Newsgroups: sci.electronics,comp.lsi
From: ravin@eecg.toronto.edu (Govindan Ravindran)
Subject: decoupling caps - onboard
Message-ID: <1993Apr20.173652.762@jarvis.csri.toronto.edu>
Organization: Department of Electrical and Computer Engineering, University of Toronto
Date: 20 Apr 93 21:36:52 GMT
Lines: 10

(posted for a friend)
hello there,
        I would like to know if any one had any experience with having
on-board decoupling capacitors (inside a cmos chip) for the power
lines. Say I have a lot of space left im my pad limited design.
any data on the effect of oxide breakdown? any info or pointers
are appreciated.

rs

