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From: richk@grebyn.com (Richard Krehbiel)
Subject: Re: WP-PCF, Linux, RISC?
In-Reply-To: ghhwang@csie.nctu.edu.tw's message of Sun, 18 Apr 1993 06:28:02 GMT
Message-ID: <1993Apr20.220900.19259@grebyn.com>
Lines: 22
Sender: richk@grebyn.com (Richard Krehbiel)
Organization: Grebyn Timesharing, Inc.
References: <C56HEo.KKA@ccu.umanitoba.ca> <C5o1yq.M34@csie.nctu.edu.tw>
Date: Tue, 20 Apr 1993 07:44:47 GMT

In article <C5o1yq.M34@csie.nctu.edu.tw> ghhwang@csie.nctu.edu.tw (ghhwang) writes:

>   Dear friend,
>     The RISC means "reduced instruction set computer". The RISC usually has 
>   small instruction set so as to reduce the circuit complex and can increase 
>   the clock rate to have a high performance. You can read some books about
>   computer architecture for more information about RISC.

RISC used to mean "Reduced Instruction Set Computer", true.  They
still use the same acronym, but only to be familiar.  What RISC really
means is a recently-designed CPU.  :-)

In general, most RISC CPUs are like this:

    A large number (32 or more) of general-purpose registers
    A fixed instruction size, usually 32 bits
    An instruction may make only one memory reference
    Memory references must be aligned
    There are delayed branches (branch after the next instruction) or
a target prediction bit (probably will/won't branch)
    Instructions may complete out of order relative to the instruction
stream
-- 
Richard Krehbiel                                 richk@grebyn.com
OS/2 2.0 will do for me until AmigaDOS for the 386 comes along...
